IJIRCSTJournal International Journal of Innovative Research in Computer Science and Technology I S Volume 2 Issue 4 Electronics and Communication English July - August 2014 N N Y 2019 11 17 Computer Sciences Free Area Estimator for Simulated Annealing of VLSI Floor Plans English Y 52 55 Ashwini Baligatti English Y Ashwini Desai English N Dr. Uday Wali English N VLSI floor planning problem encounter large dynamically changing decision trees and is known to be a NP Hard problem. Near optimal results can be obtained by non-deterministic methods such as simulated annealing. Annealing can be simulated as a stochastic process with several known and un-known variables in the process. Estimation of area for movement of individual modules at a given temperature depends on many physical parameters assigned to individual modules. In such a scenario, estimating free area within which a module can move at a given temperature is the prime factor that decides behavior of simulated annealing. We have implemented a new ‘free area estimator’ that helps improve performance of simulated annealing algorithms. Some of the simulation results have been reported. English Floorplan, Simulated Annealing, Temperature, Free area estimation https://ijircst.org/abstract.php?article_id=88