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<ArticleSet>
  <Article>
    <Journal>
      <PublisherName>IJIRCSTJournal</PublisherName>
      <JournalTitle>International Journal of Innovative Research in Computer Science and Technology</JournalTitle>
      <PISSN>I</PISSN>
      <EISSN>S</EISSN>
      <Volume-Issue>Volume 2 Issue 4</Volume-Issue>
      <PartNumber/>
      <IssueTopic> electronics and telecommunication Engg</IssueTopic>
      <IssueLanguage>English</IssueLanguage>
      <Season>July - August 2014</Season>
      <SpecialIssue>N</SpecialIssue>
      <SupplementaryIssue>N</SupplementaryIssue>
      <IssueOA>Y</IssueOA>
      <PubDate>
        <Year>2019</Year>
        <Month>11</Month>
        <Day>17</Day>
      </PubDate>
      <ArticleType>Computer Sciences</ArticleType>
      <ArticleTitle>A Novel Solution to the Synchronization Problem of CAN</ArticleTitle>
      <SubTitle/>
      <ArticleLanguage>English</ArticleLanguage>
      <ArticleOA>Y</ArticleOA>
      <FirstPage>69</FirstPage>
      <LastPage>72</LastPage>
      <AuthorList>
        <Author>
          <FirstName>Ms. Shilpa Mayannavar</FirstName>          
          <AuthorLanguage>English</AuthorLanguage>
          <Affiliation/>
          <CorrespondingAuthor>Y</CorrespondingAuthor>
          <ORCID/>
                      <FirstName>Prof. Ashwini Desai</FirstName>          
          <AuthorLanguage>English</AuthorLanguage>
          <Affiliation/>
          <CorrespondingAuthor>N</CorrespondingAuthor>
          <ORCID/>
                    <FirstName>Dr. Uday Wali</FirstName>          
          <AuthorLanguage>English</AuthorLanguage>
          <Affiliation/>
          <CorrespondingAuthor>N</CorrespondingAuthor>
          <ORCID/>
           
        </Author>
      </AuthorList>
      <DOI></DOI>
      <Abstract>One of the main problems in synchronous digital system design is synchronization of different clocks in the system. Obviously, this problem is always present in CAN bus related equipment. The problem is more acute in CAN compared to other high speed serial protocols like I2C and SPI. Speed of communication is pre-negotiated but synchronization is provided by the data frame. No separate clock line is provided. We have implemented a CAN transceiver that can automatically detect the speed and synchronization from the data frame. We have approached the problem in two distinct steps. First step is to identify the baud rate. In the following step, which is applied to every frame independently, the sampling time is adjusted with respected to the frame clock. The method also adjusts the sampling rate to reduce the number of samples required to sense the input signal. We also use a novel bit-central-sampling scheme to increase the reliability of data reading.</Abstract>
      <AbstractLanguage>English</AbstractLanguage>
      <Keywords>CAN (Controller Area Network), Frame synchronization, I2C (Inter Integrated Circuits), SPI (Serial Peripheral Interface)</Keywords>
      <URLs>
        <Abstract>https://ijircst.org/abstract.php?article_id=92</Abstract>
      </URLs>      
    </Journal>
  </Article>
</ArticleSet>