A Hardware Efficient FIR Filter for Wireless Sensor Networks
Ch. A. Swamy , I. AdumBabu, J.Narendar
Finite-impulse response (FIR) Filter is widely used in wireless sensor networks as a signal pre-processing step. Because sensor nodes require a long working periods and ultra-low cost, traditional FIR structures are in applicable as multipliers occupy too much die size for such node’s chips. This paper proposes novel FIR filter structures used in the design of application specific integrated circuits (ASICs) for sensor nodes, which can reduce the hardware cost to a minimum. The experiments show that the proposed FIR structure can lead to significant hardware savings from the traditional FIR filter. It’s a better choice for sensor node ASICs
Digital signal processing (DSP), application specific integrated circuits (ASICs), finite-impulse response (FIR) algorithm, very large scale integration (VLSI).
C. Cheng and K. K. Parhi, "Hardware efficient fast parallel FIR filter structures based on iterated short convolution," IEEE Trans. Circuits Syst. I, Reg. Paper, vol.51, no.8, pp. 1492-1500, Aug. 2004.  J. G. Chung and K. K. Parhi, “Frequency-spectrum-based low-area lowpower parallel FIR filter design,”EUROSIP J. A ppl. Signal Process., vol. 2012, no. 9, pp, 444-453,2002  Z.J. Mou and P. Duhamel, “Short-length FIR filters and their use in fast nonrecursive filtering,” IEEE Trans. Signal Process., vol. 39, no.6, pp. 1322-1332, Jun. 1991..  C. Cheng and K. K. Parhi, “Further complexity reduction of parallel FIR filters,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS 2005), Kobe, Japan, May 2005.  C. Cheng and K. K. Parhi, “Low-cost parallel FIR structures with 2- stage parallelism,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol.54, no.2, pp.280-290, Feb. 2007.  Y. Tsao and K. Choi, “Area-efficient parallel FIR digital filter structures for symmetric convolutions based on fast FIR algorithm,” IEEE Trans. VLSI Syst., vol., 20, no.2, pp. 366-371, Feb. 2012  Y. Wang and K. Roy, “CSDC: A new complexity reduction technique for multiplierless implementation of digital FIR filters,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 9, pp. 1845- 1853, Sep. 2005. H. Lee, J. Chung, and G. Sobelman, “FPGA-based digitserial CSD FIR filter for image signal format conversion,” in Proc. Int. Conf. Signal Processing Application Technology (ICSPAT’98), Toronto, ON. Canada, Sept 1998.  M. Martinez-Peiro, E. Boemo, and L. Wanhammer, “Design of highspeed multiplierless filters using a nonrecursive signed common subexpression algorithm,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 49, no. 3, pp. 196-203, Mar. 2002.  K. Muhammad and K. Roy, “A graph theoretic approach for synthesizing very low-complexity high-speed digital filters,” IEEE Trans. Comp.-Aided Des. Integr. Circuits, vol. 21, no. 2, pp. 204- 216, Feb. 2002. 201
[Ch. A. Swamy , I. AdumBabu, J.Narendar (2014) A Hardware Efficient FIR Filter for Wireless Sensor Networks IJIRCST Vol-2 Issue-3 Page No-61-66] (ISSN 2347 - 5552). www.ijircst.org
Ch. A. Swamy
Assistant Professor, MLRITM, Dundigal ( firstname.lastname@example.org)