Algorithm for Low Power IO port Design by Using CGT
Dr C. M. Jadhao
The Clock power is a major component of microprocessor power mainly because the clock is fed to most of the circuit blocks in the processor, and the clock switches every cycle. Thus the total clock power is a substantial component of total microprocessor power dissipation. Clockgating is a well-known technique to reduce clock power. Because individual circuit usage varies within and across applications, not all the circuits are used all the time, giving rise to power reduction opportunity. By ANDing the clock with a gate-control signal, clock-gating essentially disables the clock to a circuit whenever the circuit is not used, avoiding power dissipation due to unnecessary charging and discharging of the unused circuits. Specifically, clock-gating targets the clock power consumed in pipeline latches and dynamic-CMOS-logic circuits (e.g., integer units, floatingpoint units, and word-line decoders of caches) used for speed and area advantages over static logic. Clock gating is a wellknown technique to reduce chip dynamic power. This paper propose a modified clockgating techniques based on ACG(Adaptive Clock Gating) and instruction level clock gating. The proposed clock gatingtechnique reduces not only switching activity of functional blocks in IDLE state but also dynamic power in running state. Modified ACG can automatically enable or disable the clock of the functional block. The experimental results onsome I/O port core in SoC show an average of 19.45% dynamic power reduction comparing to previous ACG technique. With the scaling of technology and the need for higher performance and more functionality, power dissipation is becoming a major bottleneck for microprocessor designs. Clock power is significant in high-performance processors.
ACG, DCG, IO Ports, CMOS, Low Power
 Hai Li; Bhunia, S. Yiran Chen Roy, K. Vijaykumar, T.N. DCG: deterministic clock-gating for low-power microprocessor design; IEEE Transactions on Very Large Scale Integration(VLSI) Systems; Volume 12, Issue 3, March 2004 Page(s):245-254
 Xiaotao Chang, Adaptive Clock Gating Technique for Low Power IP Core in SoC Design, Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on, 120-2123, May 2007
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[Dr C. M. Jadhao (2014) Algorithm for Low Power IO port Design by Using CGT IJIRCST Vol-2 Issue-2 Page No-1-4] (ISSN 2347 - 5552). www.ijircst.org
Dr C. M. Jadhao
Principal, Mauli College of Engineering, Shegaon444203, India (email: firstname.lastname@example.org)