Adder is an inevitable circuit in any of the VLSI Designs. Since, the arithmetic operations such as subtraction, multiplication and division depends on the operation of addition, adder is dubbed as heart of any Digital Signal Processor (DSP), microprocessor and VLSI Architecture. In this report, the logic formulations in regular carry select adder (CSLA) and binary to excess 1 converter (BEC) based CSLA are analysed and the data dependency, redundant logic operations were scrutinized to improve the Area-Delay Product (ADP). All the redundant logic operations identified were removed and a new logic formulation has been proposed for the CSLA based on data dependency. In the proposed arrangement, the carry select (CS) operation is carried out before calculation of final-sum. Carry input for various selections (corresponding toCin= 0and 1) and fixed Cin bits are used for logic optimization of CG and CS units. An efficient CSLA scheme is obtained using optimized logic units using BEC based CSLA Approach. The proposed CSLA design provides significant values of area and delay than the recently proposed CSLAs. Due to a small carry-output delay, the proposed CSLA design is well suited for square-root (SQRT) based variable CSLA Approach. Simulation results shows that the proposed SQRT-CSLA involves nearly 42% less area– delay–product (ADP) than the existing CSLAs. This is best among the existing CSLA designs for different bit-widths (128, 64, 32 and 16). Area in terms of logical elements and the delay in nano-seconds were obtained through Xilinx ISE 13.2 Version
