Because there are more data bits and memory operations in modern digital networks, data transport and reception are more complicated, resulting in more data loss and lower throughputs. As a result, the suggested work of this study uses the Canonical Huffman compression approach to deliver lossless data compression with minimal memory architecture. The Huffman machine will present a memory-efficient design that is lossless and supports multi-bit data compression [1]. Here, utilizing variable length and the Canonical Huffman encoding method, this methodology will show input as 640 data bits, compressed output as 90 data bits, and de-compressor 90 data bits to 640 data bits using the Canonical Huffman decoding method. Finally, this work will be synthesized on a Vertex FPGA and presented in Verilog HDL, with results for area, delay, and power.
Keywords
Data Bits, Decoding, Decompression, Logic Gates, Throughput, Canonical Huffman Compression in Verilog HDL
