2:1 Multiplexer Design Using Lector, LCnmos, LCpmos Power Reduction Techniques with 45nm, 90nm, 180nm CMOS Technology

Dr. Ch. Manohar Kumar; Ms. M.V. Sree Harika; Mr. S. Mahesh Babu; Ms. D. Manasa Lakshmi; Mr. G. Jagadeesh

doi:10.55524/ijircst.2022.10.3.4

Abstract

Today’s modern communication requires high data transmission rate and low power consumption. One of the most common concepts of data transmission can be achieved by Multiplexers. The Multiplexers are the logic designs where data can be transmitted by n number of inputs over the transmission path based on the selection line producing the single input. The application of Multiplexers is more active in communications systems. Also Low power consumption and the high-speed result is the major concern for choosing the digital circuits [1,2]. Here we designed a 2:1 Multiplexer using CMOS technology with 45nm, 90nm, and 180nm. Since CMOS offers less power consumption, we can till reduce the power consumed by using power reduction techniques. In this paper we designed and compared the 2:1 Multiplexer using Lector, LCnmos, and LCpmos power reduction techniques.

Keywords

Multiplexer, CMOS technology, Lector technique, LCnmos technique and LCpmos technique

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Cites this article as

C. M. Kumar, M. M. S. Harika, M. S. M. Babu, M. D. M. Lakshmi, M. G. Jagadeesh, "2:1 Multiplexer Design Using Lector, LCnmos, LCpmos Power Reduction Techniques with 45nm, 90nm, 180nm CMOS Technology", International Journal of Innovative Research in Engineering & Management (ijircst), Vol-10, Issue-3, Page No-12-21, 2022. Available from: https://doi.org/10.55524/ijircst.2022.10.3.4

Corresponding Author

Ch. Manohar Kumar

Assistant Professor, Department of Electronics and Communication Engineering, Gayatri Vidya Parishad College for Degree and PG Courses(A), Visakhapatnam, Andhra Pradesh, India

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