Verilog HDL using LTE Implementation MAP Algorithm

T. Rama Krishna; T. Krishna Murthy; N. Vilasrao Sarode; P. Srilakshmi; V. Geetha Sri

doi:10.55524/ijircst.2022.10.2.115

Abstract

In many communication systems, turbo coding Techniques for Encoding and Decoding are employed to repair errors. As compared to other error correction codes, turbo codes provide great error correcting capabilities. For the implementation of the Turbo decoder, a Very Large Scale Integration (VLSI) architecture is suggested in this study. The Maximum-a-Posteriori (MAP) algorithm is employed at the decoder side, where soft-in-soft-out decoders, interleaves, and deinterleavers are all used. The usage of the MAP algorithm reduces the quantity of iterations necessary to decode the information bits being transferred. This research employs a system for the encoder component that consists of two recursive convolutional encoders and a pseudorandom interleaver on the encoder side. Tools from Octave and Xilinx Vivado are used for the Turbo encoding and decoding. The system is synthesised and implemented using a specialised integrated circuit.

Keywords

Encoding, Decoding Techniques. MAP, Xilinx, vivado.

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Cites this article as

T. R. Krishna, T. K. Murthy, N. V. S. , P. Srilakshmi, V. G. Sri, "Verilog HDL using LTE Implementation MAP Algorithm", International Journal of Innovative Research in Engineering & Management (ijircst), Vol-10, Issue-2, Page No-611- 614, 2022. Available from: https://doi.org/10.55524/ijircst.2022.10.2.115

Corresponding Author

T. Rama Krishna

Associate Professor, Department of Electronics and Communications Engineering, PACE Institute of Technology & Sciences, Ongole, Andhra Pradesh, India

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