Design and Implementation of Two Speed Multiplier Using FPGA

U. Anusha Rani; Kotte Chandrika; Ardaveeti Ranga Manikanta; Chimmiri Dorababu; Naga Sudheer Rajavarapu; Muvva Gopi

Abstract

Multiplication has recently been given top priority in all applications of digital signal processing and machine learning. It is crucial to control the area, latency, power, and performance overall using parallel implementations. This will require more logic sizes with critical routes and more power consumption because the amount of multiplications will also result in a number of arithmetic additions and subtractions. In order to address this issue, the proposed work will present extensive optimization of radix-4 multiplication circuits using a modified booth algorithm and a kogge stone adder, which will result in smaller critical paths and improved performance overall when compared to Wallace trees and DADDA multipliers. Finally, this effort will synthesize in a Xilinx FPGA using Verilog HDL and demonstrate area comparisons.

Keywords

FPGA, Verilog HDL, DADDA multipliers, DFT, DCT

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Cites this article as

U. A. Rani, K. Chandrika, A. R. Manikanta, C. Dorababu, N. S. Rajavarapu, M. Gopi, "Design and Implementation of Two Speed Multiplier Using FPGA", International Journal of Innovative Research in Computer Science and Technology (IJIRCST), Vol-11, no.4, pp.74-77, 2023. Available from: https://doi.org/10.55524/ijircst.2023.11.4.13

Corresponding Author

U. Anusha Rani

Assistant Professor, Department of Electronics and Communication Engineering, PACE Institute of Technology and Sciences, Ongole, Andhra Pradesh, India.

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Design and Implementation of Two Speed Multiplier Using FPGA

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