FPGA Implementation of High Throughput Lossless Canonical Huffman Machine Decoder

P. Uday Kumar; K.Vineela; J.venkatavamsi; N.Rajesh; R.V. Lokesh kumar; Lokesh kumar; P.Hyndavi

Abstract

Because there are more data bits and memory operations in modern digital networks, data transport and reception are more complicated, resulting in more data loss and lower throughputs. As a result, the suggested work of this study uses the Canonical Huffman compression approach to deliver lossless data compression with minimal memory architecture. The Huffman machine will present a memory-efficient design that is lossless and supports multi-bit data compression [1]. Here, utilizing variable length and the Canonical Huffman encoding method, this methodology will show input as 640 data bits, compressed output as 90 data bits, and de-compressor 90 data bits to 640 data bits using the Canonical Huffman decoding method. Finally, this work will be synthesized on a Vertex FPGA and presented in Verilog HDL, with results for area, delay, and power.

Keywords

Data Bits, Decoding, Decompression, Logic Gates, Throughput, Canonical Huffman Compression in Verilog HDL

References

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Cites this article as

P. U. Kumar, K.Vineela, J.venkatavamsi, N.Rajesh, R. L. kumar, L. kumar, P.Hyndavi, "FPGA Implementation of High Throughput Lossless Canonical Huffman Machine Decoder", International Journal of Innovative Research in Computer Science and Technology (IJIRCST), Vol-11, no.4, pp.78-81, 2023. Available from: https://doi.org/10.55524/ijircst.2023.11.4.14

Corresponding Author

P. Uday Kumar

Assistant Professor, Department of Electronics and Communication Engineering, PACE Institute of Technology and Sciences, Ongole, Andhra Pradesh, India

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FPGA Implementation of High Throughput Lossless Canonical Huffman Machine Decoder

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