Design Verification in VLSI is the most important step in the product development process. It aims to confirm that the system design meets with the standards and requirements of the system. Verification is the process of checking whether the designed system performs all the required functionality specified in the design by writing the test bench or verification environment that contains a group of classes and modules that generates input stimulus to the system and the output from that design is compared with the expected output.  A communication system has set of roles that are called protocols. UART is a serial communication protocol that is used when only two devices are needed to communicate and it uses peer-to-peer topology. I2C stands for Inter-Integrated Circuit used for communication between master and slave in which more than one slave device or memory can be connected to a master device. System Verilog has been primarily used for verification purposes in VLSI because it has the features of Hardware Description Languages such as Verilog and VHDL, C and C++ and functional coverage, assertion coverage, constrained randomization, and supports OOPs concepts.