A high performance hardware FFT have numerous application in instrumentation and communication systems. It describes new parallel FFT architecture which combines the split-radix algorithm with a constant geometry interconnect structure. The split-radix algorithm knows to have lower multiplicative complexity than both radix-2 as well as radix-4 algorithm. The split-radix algorithm maps onto a constant geometry interconnect structure in which the wiring in each FFT stage is indistinguishable, resulting in low multiplexing overhead. We are exploiting the lower arithmetic complexity of split-radix to lower dynamic energy, by gating the multipliers during trivial multiplication. The proposed FFT accomplishes less power than a parallel radix-4 design when computing at some point, the real-valued transform.